# D-Wave QPU Architecture: Topologies¶

The layout of the D-Wave QPU is critical to translating a QUBO or Ising objective function into a format that a D-Wave system can solve. You now know that binary objective functions can be represented as graphs; this chapter explains the mapping between a problem graph and the QPU topology.

Note

Although Ocean software automates this mapping, you should understand it if you are directly programming the QPU because it has implications for the problem-graph size and solution quality. If you are sending your problem to a Leap quantum-classical hybrid solver, the solver handles all interactions with the QPU.

Leap hybrid solvers are described here: Leap’s Hybrid Solvers

The D-Wave quantum processing unit (QPU) is a lattice of interconnected qubits.
While some qubits connect to others via couplers, the D-Wave QPU is not fully
connected. Instead, the qubits of D-Wave 2000Q and earlier generations of QPUs
interconnect in a topology known as *Chimera* while Advantage QPUs incorporate
the *Pegasus* topology.

Some small number of qubits and couplers in a QPU may not meet the specifications
to function as desired. These are therefore removed from the programmable fabric
that users can access. The subset of the Pegasus or Chimera graph available to
users is the *working graph*. The yield[1] of the working graph is the percentage
of working qubits that are present.

[1] | Manufacturing variations and the need to prepare the QPU to operate at cryogenic temperatures in a low–magnetic field environment limits the yield. These variations are minimized through an extensive calibration process that attempts to bring all of these analog devices into a consistent parametric regime. For example, each D-Wave 2000Q QPU is fabricated with 2048 qubits and 6016 couplers in a Chimera topology. Of this total, the number and specific set of qubits and couplers that can be made available in the working graph changes with each system cooldown and calibration cycle. Calibrated commercial systems typically have more than 97% of fabricated qubits available in their working graphs. |

## Chimera Graph¶

In the D-Wave 2000Q and earlier systems, qubits are “oriented” on the QPU vertically or horizontally as shown in Figure 11.

For QPUs with the Chimera topology it is conceptually useful to categorize couplers as follows:

**Internal couplers**.Internal couplers connect pairs of orthogonal (with opposite orientation) qubits as shown in Figure 12. The Chimera topology has a recurring structure of four horizontal qubits coupled to four vertical qubits in a \(K_{4,4}\) bipartite graph, called a

*unit cell*.A unit cell is typically rendered as either a cross or a column as shown in Figure 13.

**External couplers**.External couplers connect colinear pairs of qubits—pairs of parallel qubits in the same row or column—as shown in Figure 14.

The \(K_{4,4}\) unit cells formed by internal couplers are connected by external couplers as a lattice: this is the Chimera topology. Figure 15 shows two unit cells that form part of a larger Chimera graph.

Chimera qubits are characterized as having:

- nominal length 4—each qubit is connected to 4 orthogonal qubits through internal couplers
- degree 6—each qubit is coupled to 6 different qubits

The notation CN refers to a Chimera graph consisting of an \(N{\rm x}N\) grid of unit cells. The D-Wave 2000Q QPU supports a C16 Chimera graph: its more than 2000 qubits are logically mapped into a \(16 {\rm x} 16\) matrix of unit cells of 8 qubits. The \(2 {\rm x} 2\) Chimera graph of Figure 12 is denoted C2.

## Pegasus Graph¶

In the Pegasus topology, qubits are “oriented” vertically or horizontally, as in Chimera, but similarly aligned qubits are also shifted, as illustrated in Figure 16.

For QPUs with the Pegasus topology it is conceptually useful to categorize couplers as internal, external, and odd. Figure 17 and Figure 18 show two views of the coupling of qubits in this topology.

### Pegasus Couplers¶

**Internal couplers**.Internal couplers connect pairs of orthogonal (with opposite orientation) qubits as shown in Figure 19. Each qubit is connected via internal coupling to 12 other qubits.

**External couplers**.External couplers connect vertical qubits to adjacent vertical qubits and horizontal qubits to adjacent horizontal qubits as shown in Figure 20.

**Odd couplers**.Odd couplers connect similarly aligned pairs of qubits as shown in Figure 21.

Pegasus features qubits of degree 15 and native \(K_4\) and \(K_{6,6}\) subgraphs. Pegasus qubits are considered to have a nominal length of 12 (each qubit is connected to 12 orthogonal qubits through internal couplers) and degree of 15 (each qubit is coupled to 15 different qubits).

As the notation \(C_n\) refers to a Chimera graph with size parameter N, \(P_n\) refers to instances of Pegasus topologies; for example, \(P_3\) is a graph with 144 nodes. A Pegasus unit cell contains twenty-four qubits, with each qubit coupled to one similarly aligned qubit in the cell and two similarly aligned qubits in adjacent cells, as shown in Figure 22. An Advantage QPU is a lattice of \(16x16\) such unit cells, denoted as a \(P_{16}\) Pegasus graph.

More formally, the Pegasus unit cell consists of 48 halves of qubits that are divided between adjacent such unit cells, as shown in Figure 23.